seg71

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 1KB
Downloads: 6
Upload time: 2010-11-28 10:03:18
Uploader: riversky
Description:   7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to the user multiple digital dynamic display method. Dynamic display method is to rotate at a certain frequency of the various digital control of the COM to send low end, while the corresponding data sent to each segment.

File list:
seg71.v,2157,2005-11-23

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