interlace

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 1KB
Downloads: 39
Upload time: 2010-11-26 19:33:18
Uploader: Naruto65
Description:   In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can also be deinterleaving deinterleaving pattern, the same algorithm.

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interlace.v,5051,2010-11-10

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