Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 1KB
Downloads: 39
Upload time: 2010-11-26 19:33:18
Uploader: Naruto65
Description:   In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can also be deinterleaving deinterleaving pattern, the same algorithm.

File list:

Download users:

Relate files:

Comment: Add Comment

Favorite users: