Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 2KB
Downloads: 10
Upload time: 2010-10-15 10:40:07
Uploader: 周宽裕
Description:   A return to the Manchester encoded signal is input into the actual data mdi and stored in the dual-port RAM notify the DSP after the break to read the data, the required dual-port RAM from the corresponding FPGA program can be generated build system

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