EDA3add

Directory: VHDL-FPGA-Verilog
Plat: VHDL
Size: 176KB
Downloads: 15
Upload time: 2010-10-08 00:05:19
Uploader: 周旋
Description:   Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of the detector, the first design (schematic diagram input) sequence signal generator sequence: 0111010011011010 re-design of the detector, if the detected serial Series 11010 output is " 1" , otherwise the output is " 0" , and its simulation and hardware testing.

File list:
EDA3add
.......\db
.......\..\add_sub_klh.tdf,2431,2009-10-30
.......\..\prev_cmp_SCHK.asm.qmsg,1991,2009-10-30
.......\..\prev_cmp_SCHK.fit.qmsg,5002,2009-10-30
.......\..\prev_cmp_SCHK.map.qmsg,6296,2009-10-30
.......\..\prev_cmp_SCHK.qmsg,8552,2009-10-30
.......\..\prev_cmp_SCHK.sim.qmsg,3604,2009-10-30
.......\..\prev_cmp_SCHK.tan.qmsg,34300,2009-10-30
.......\..\SCHK.asm.qmsg,1991,2009-10-30
.......\..\SCHK.cbx.xml,178,2009-10-30
.......\..\SCHK.cmp.cdb,5484,2009-10-30
.......\..\SCHK.cmp.hdb,8772,2009-10-30
.......\..\SCHK.cmp.logdb,4,2009-10-30
.......\..\SCHK.cmp.rdb,13192,2009-10-30
.......\..\SCHK.cmp.tdb,4045,2009-10-30
.......\..\SCHK.cmp0.ddb,3720,2009-10-30
.......\..\SCHK.db_info,137,2009-10-30
.......\..\SCHK.eco.cdb,161,2009-10-30
.......\..\SCHK.eds_overflow,3,2009-10-30
.......\..\SCHK.fit.qmsg,5002,2009-10-30
.......\..\SCHK.fnsim.cdb,3942,2009-10-30
.......\..\SCHK.fnsim.hdb,12773,2009-10-30
.......\..\SCHK.fnsim.qmsg,8552,2009-10-30
.......\..\SCHK.hier_info,1137,2009-10-30
.......\..\SCHK.hif,4402,2009-10-30
.......\..\SCHK.lpc.html,430,2009-10-30
.......\..\SCHK.lpc.rdb,385,2009-10-30
.......\..\SCHK.lpc.txt,1060,2009-10-30
.......\..\SCHK.map.cdb,2407,2009-10-30
.......\..\SCHK.map.hdb,8678,2009-10-30
.......\..\SCHK.map.logdb,4,2009-10-30
.......\..\SCHK.map.qmsg,6296,2009-10-30
.......\..\SCHK.pre_map.cdb,3437,2009-10-30
.......\..\SCHK.pre_map.hdb,7255,2009-10-30
.......\..\SCHK.rpp.qmsg,1823,2009-10-30
.......\..\SCHK.rtlv.hdb,7236,2009-10-30
.......\..\SCHK.rtlv_sg.cdb,3342,2009-10-30
.......\..\SCHK.rtlv_sg_swap.cdb,178,2009-10-30
.......\..\SCHK.sgate.rvd,1906,2009-10-30
.......\..\SCHK.sgate_sm.rvd,1947,2009-10-30
.......\..\SCHK.sgdiff.cdb,2758,2009-10-30
.......\..\SCHK.sgdiff.hdb,10916,2009-10-30
.......\..\SCHK.sim.cvwf,1380,2009-10-30
.......\..\SCHK.sim.hdb,3004,2009-10-30
.......\..\SCHK.sim.qmsg,3604,2009-10-30
.......\..\SCHK.sim.rdb,3393,2009-10-30
.......\..\SCHK.simfam,10,2009-10-30
.......\..\SCHK.sld_design_entry.sci,154,2009-10-30
.......\..\SCHK.sld_design_entry_dsc.sci,154,2009-10-30
.......\..\SCHK.smp_dump.txt,191,2009-10-30
.......\..\SCHK.syn_hier_info,0,2009-10-30
.......\..\SCHK.tan.qmsg,34944,2009-10-30
.......\..\SCHK.tis_db_list.ddb,174,2009-10-30
.......\..\SCHK.tmw_info,304,2009-10-30
.......\..\wed.wsf,5574,2009-10-30
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\SCHK.root_partition.map.kpt,7822,2009-10-30
.......\..............\README,653,2009-10-30
.......\SCHK.asm.rpt,6929,2009-10-30
.......\SCHK.done,26,2009-10-30
.......\SCHK.fit.rpt,38449,2009-10-30
.......\SCHK.fit.summary,368,2009-10-30
.......\SCHK.flow.rpt,6622,2009-10-30
.......\SCHK.map.rpt,22000,2009-10-30
.......\SCHK.map.summary,284,2009-10-30
.......\SCHK.pin,25681,2009-10-30
.......\SCHK.pof,212109,2009-10-30
.......\SCHK.qpf,1264,2009-10-30
.......\SCHK.qsf,2326,2009-10-30
.......\SCHK.qws,554,2009-10-30
.......\SCHK.sim.rpt,31644,2009-10-30
.......\SCHK.sof,164201,2009-10-30
.......\SCHK.tan.rpt,32285,2009-10-30
.......\SCHK.tan.summary,1594,2009-10-30
.......\SCHK.vhd,2760,2009-10-30
.......\SCHK.vwf,9196,2009-10-30

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