qipan

Directory: VHDL-FPGA-Verilog
Plat: Others
Size: 80KB
Downloads: 12
Upload time: 2010-07-28 14:36:13
Uploader: 怜香断
Description:   The program is under QuartusII prepared using VHDL display board in SOPC platform for cell function code. Useful, are welcome to download.

File list:
qipan
.....\a.bsf,4971,2009-03-03
.....\aa.asm.rpt,7550,2010-05-26
.....\aa.bdf,16074,2010-05-26
.....\aa.cdf,294,2010-05-26
.....\aa.done,26,2010-05-26
.....\aa.fit.eqn,34005,2010-05-26
.....\aa.fit.rpt,96971,2010-05-26
.....\aa.fit.summary,401,2010-05-26
.....\aa.flow.rpt,3656,2010-05-26
.....\aa.map.eqn,22561,2010-05-26
.....\aa.map.rpt,21112,2010-05-26
.....\aa.map.summary,311,2010-05-26
.....\aa.pin,30250,2010-05-26
.....\aa.pof,524489,2010-05-26
.....\aa.qpf,898,2009-04-25
.....\aa.qsf,3827,2010-07-28
.....\aa.qws,1640,2010-07-28
.....\aa.sim.rpt,126961,2009-02-18
.....\aa.sof,140520,2010-05-26
.....\aa.tan.rpt,47477,2010-05-26
.....\aa.tan.summary,1686,2010-05-26
.....\aa.vwf,28493,2009-02-18
.....\aa_assignment_defaults.qdf,29662,2010-02-05
.....\b.bsf,2173,2009-03-03
.....\db
.....\..\aa.db_info,136,2010-06-05
.....\..\aa.eco.cdb,160,2010-07-28
.....\..\aa.sld_design_entry.sci,153,2010-07-28
.....\..\add_sub_3nh.tdf,2743,2009-02-16
.....\..\add_sub_5nh.tdf,3057,2009-02-16
.....\..\add_sub_6nh.tdf,3215,2009-02-12
.....\..\add_sub_cch.tdf,3081,2009-02-16
.....\..\add_sub_foh.tdf,3547,2009-02-12
.....\..\add_sub_goh.tdf,3718,2009-02-12
.....\heng.bsf,1952,2010-05-26
.....\heng.vhd,856,2010-05-26
.....\huo.bsf,1799,2010-05-26
.....\huo.vhd,385,2010-05-26
.....\output_file.map,129,2009-05-28
.....\output_file.pof,131258,2009-05-28
.....\shu.bsf,1951,2010-05-26
.....\shu.vhd,721,2010-05-26
.....\sopc_builder_debug_log.txt,76,2009-02-16
.....\Waveform1.vwf,18328,2009-02-18

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