des-verilog

Directory: VHDL-FPGA-Verilog
Plat: Windows_Unix
Size: 66KB
Downloads: 259
Upload time: 2005-09-19 11:19:36
Uploader: 杨云丰
Description:   des encryption algorithm to achieve the Verilog language

File list:
des
...\des
...\...\bench
...\...\.....\CVS
...\...\.....\...\Entries
...\...\.....\...\Repository
...\...\.....\...\Root
...\...\.....\verilog
...\...\.....\.......\CVS
...\...\.....\.......\...\Entries
...\...\.....\.......\...\Repository
...\...\.....\.......\...\Root
...\...\.....\.......\des3_test_ao.v
...\...\.....\.......\des3_test_po.v
...\...\.....\.......\des_test_ao.v
...\...\.....\.......\des_test_po.v
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\doc
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\README.txt
...\...\rtl
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\verilog
...\...\...\.......\area_opt
...\...\...\.......\........\CVS
...\...\...\.......\........\...\Entries
...\...\...\.......\........\...\Repository
...\...\...\.......\........\...\Root
...\...\...\.......\........\des.v
...\...\...\.......\........\des3.v
...\...\...\.......\........\key_sel.v
...\...\...\.......\........\key_sel3.v
...\...\...\.......\common
...\...\...\.......\......\crp.v
...\...\...\.......\......\CVS
...\...\...\.......\......\...\Entries
...\...\...\.......\......\...\Repository
...\...\...\.......\......\...\Root
...\...\...\.......\......\sbox1.v
...\...\...\.......\......\sbox2.v
...\...\...\.......\......\sbox3.v
...\...\...\.......\......\sbox4.v
...\...\...\.......\......\sbox5.v
...\...\...\.......\......\sbox6.v
...\...\...\.......\......\sbox7.v
...\...\...\.......\......\sbox8.v
...\...\...\.......\CVS
...\...\...\.......\...\Entries
...\...\...\.......\...\Repository
...\...\...\.......\...\Root
...\...\...\.......\perf_opt
...\...\...\.......\........\CVS
...\...\...\.......\........\...\Entries
...\...\...\.......\........\...\Repository
...\...\...\.......\........\...\Root
...\...\...\.......\........\des.v
...\...\...\.......\........\des3.v
...\...\...\.......\........\key_sel.v
...\...\sim
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\rtl_sim
...\...\...\.......\bin
...\...\...\.......\...\CVS
...\...\...\.......\...\...\Entries
...\...\...\.......\...\...\Repository
...\...\...\.......\...\...\Root
...\...\...\.......\...\Makefile
...\...\...\.......\CVS
...\...\...\.......\...\Entries
...\...\...\.......\...\Repository
...\...\...\.......\...\Root
...\...\...\.......\run
...\...\...\.......\...\CVS
...\...\...\.......\...\...\Entries
...\...\...\.......\...\...\Repository
...\...\...\.......\...\...\Root
...\...\syn
...\...\...\bin
...\...\...\...\comp_ao.dc
...\...\...\...\comp_ao3.dc
...\...\...\...\comp_po.dc
...\...\...\...\comp_po3.dc
...\...\...\...\CVS
...\...\...\...\...\Entries
...\...\...\...\...\Repository
...\...\...\...\...\Root
...\...\...\...\design_spec_ao.dc
...\...\...\...\design_spec_ao3.dc

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